Visible to Intel only — GUID: nik1398984198758
Ixiasoft
Visible to Intel only — GUID: nik1398984198758
Ixiasoft
12.10. Optional Reset Control and Status Interfaces for Deterministic Latency PHY
The following table describes the signals in the optional reset control and status interface. These signals are available if you do not enable the embedded reset controller.
Signal Name | Direction | Description |
---|---|---|
pll_powerdown [<n>-1:0] | Input | When asserted, resets the TX PLL. |
tx_digitalreset [<n>-1:0] | Input | When asserted, reset all blocks in the TX PCS. |
tx_analogreset [<n>-1:0] | Input | When asserted, resets all blocks in the TX PMA. |
tx_cal_busy [<n>-1:0] | Output | When asserted, indicates that the initial TX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP. You must hold the channel in reset until calibration completes. |
rx_digitalreset [<n>-1:0] | Input | When asserted, resets the RX PCS. |
rx_analogreset [<n>-1:0] | Input | When asserted, resets the RX CDR. |
rx_cal_busy [<n>-1:0] | Output | When asserted, indicates that the initial RX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP. |
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