4.11. 10GBASE-KR PHY Clock and Reset Interfaces
Use the Transceiver PHY Reset Controller IP Core to automatically control the transceiver reset sequence. This reset controller also has manual overrides for the TX and RX analog and digital circuits to allow you to reset individual channels upon reconfiguration.
If you instantiate multiple channels within a transceiver bank they share TX PLLs. If a reset is applied to this PLL, it will affect all channels. Altera recommends leaving the TX PLL free-running after the start-up reset sequence is completed. After a channel is reconfigured you can simply reset the digital portions of that specific channel instead of going through the entire reset sequence. If you are not using the sequencer and the data link is lost, you must assert the rx_digitalreset when the link recovers. For more information about reset, refer to the "Transceiver PHY Reset Controller IP Core" chapter in the Altera Transceiver PHY IP Core User Guide.
The following figure provides an overview of the clocking for this core.
To ensure proper functioning of the PCS, the maximum PPM difference between the pll_ref_clk_10g and the xgmii_tx_clk clock inputs is 0 PPM.
The following table describes the clock and reset signals. The frequencies of the XGMII clocks increases to 257.8125 MHz when you enable 1588.
|rx_recovered_clk||Output||The RX clock which is recovered from the received data. You can use this clock as a reference to lock an external clock source. Its frequency is 125 or 257.8125 MHz.|
|tx_clkout_1g||Output||GMII TX clock for the 1G TX parallel data source interface. The frequency is 125 MHz.|
|rx_clkout_1g||Output||GMII RX clock for the 1G RX parallel data source interface. The frequency is 125 MHz.|
|rx_coreclkin_1g||Input||Clock to drive the read side of the RX phase compensation FIFO in the Standard PCS. The frequency is 125 MHz.|
|tx_coreclkin_1g||Input||Clock to drive the write side of the TX phase compensation FIFO in the Standard PCS. The frequency is 125 MHz.|
|pll_ref_clk_1g||Input||Reference clock for the PMA block for the 1G mode. Its frequency is 125 or 62.5 MHz.|
|pll_ref_clk_10g||Input||Reference clock for the PMA block in 10G mode. Its frequency is 644.53125 or 322.265625 MHz.|
|pll_powerdown_1g||Input||Resets the 1Gb TX PLLs.|
|pll_powerdown_10g||Input||Resets the 10Gb TX PLLs.|
|tx_analogreset||Input||Resets the analog TX portion of the transceiver PHY.|
|tx_digitalreset||Input||Resets the digital TX portion of the transceiver PHY.|
|rx_analogreset||Input||Resets the analog RX portion of the transceiver PHY.|
|rx_digitalreset||Input||Resets the digital RX portion of the transceiver PHY.|
|usr_an_lt_reset||Input||Resets only the AN and LT logic. This signal is only available for the 10GBASE‑KR variants.|
|usr_seq_reset||Input||Resets the sequencer. Initiates a PCS reconfiguration, and may restart AN, LT or both if these modes are enabled.|
|usr_fec_reset||Input||When asserted, resets the 10GBASE-KR FEC module.|
|usr_soft_10g_pcs_reset||Input||When asserted, resets the 10G PCS associated with the FEC module.|
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