19.2. Transceiver PLL Parameters
|Enable PLL Reconfiguration||On/Off||You must enable this option if you plan to reconfigure the PLLs in your design. This option is also required to simulate PLL reconfiguration.|
|Number of TX reference clocks||1-5||
Specifies the number of reference clocks inputs to the Transceiver PLL.
|PLL feedback path|| Internal
|Select the External feedback path for the CPRI protocol to improve clock jitter by using an external voltage controlled crystal oscillator (VCXO). Select Internal for all other protocols.|
|Specifies the PLL type. You must select the CMU PLL for designs that also include a fractional PLL. The ATX pll is available for Stratix V and Arria V GZ devices.|
|PLL base data rate||
1 × Lane rate
2 × Lane rate
4 × Lane rate
8 × Lane rate
|Specifies Base data rate. This value should match the value specified in the Native PHY.|
|Reference clock frequency||Variable||Specifies the frequency of the PLL input reference clock. The PLL must generate an output frequency that equals the Base data rate/2. You can use any Input clock frequency that allows the PLLs to generate this output frequency.|
|Selected reference clock source||0-4||Specifies the index of the TX reference clock for the initial configuration of the TX PLL. Logical index 0 corresponds to TX reference clock 1, and so on.|
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