V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

6.4.5. Status Signals

Table 79.  Status Signals
Signal Name Direction Clock Domain Width Description
led_char_err Output Synchronous to rx_clkout 1 Asserted when a 10-bit character error is detected in the RX data.
led_link Output Synchronous to tx_clkout 1 Asserted when the link synchronization for 1GbE or 2.5GbE is successful
led_disp_err Output Synchronous to rx_clkout 1 Asserted when a 10-bit running disparity error is detected in the RX data.
led_an Output Synchronous to rx_clkout 1 Asserted when auto-negotiation is completed.
rx_block_lock Output Synchronous to rx_clkout 1 Asserted when the link synchronization for 10GbE is successful.

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