V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

4.5. 10GBASE-KR PHY IP Core Functional Description

This topic provides high-level block diagram of the 10GBASE-KR hardware.
The following figure shows the 10GBASE‑KR PHY IP Core and the supporting modules required for integration into your system. In this figure, the colors have the following meanings:
  • Green-Altera- Cores available Intel® Quartus® Prime IP Library, including the 1G/10Gb Ethernet MAC, the Reset Controller, and Transceiver Reconfiguration Controller.
  • Orange-Arbitration Logic Requirements. Logic you must design, including the Arbiter and State Machine. Refer to 10GBASE-KR PHY Arbitration Logic Requirements and 10GBASE-KR PHY State Machine Logic Requirements for a description of this logic.
  • White - 1G,10G and AN/LT settings files that you must generate. Refer to Creating a 10GBASE-KR Design for more information.
  • Blue-The 10GBASE-KR PHY IP core available in the Intel® Quartus® Prime IP Library.
Figure 17. Detailed 10GBASE-KR PHY IP Core Block Diagram

As this figure illustrates, the 10GBASE-KR PHY is built on the Native PHY and includes the following additional blocks implemented in soft logic to implement Ethernet functionality defined in Clause 72 of IEEE 802.3ap-2007.

Link Training (LT), Clause 72

This module performs link training as defined in Clause 72. The module facilitates two features:

  • Daisy‑chain mode for non-standard link configurations where the TX and RX interfaces connect to different link partners instead of in a spoke and hub or switch topology.
  • An embedded processor mode to override the state‑machine‑based training algorithm. This mode allows an embedded processor to establish link data rates instead of establishing the link using the state‑machine‑based training algorithm.

The following figure illustrates the link training process, where the link partners exchange equalization data.

Figure 18. TX Equalization for Link Partners

TX equalization includes the following steps which are identified in this figure.

  1. The receiving link partner calculates the BER.
  2. The receiving link partner transmits an update to the transmitting link partner TX equalization parameters to optimize the TX equalization settings
  3. The transmitting partner updates its TX equalization settings.
  4. The transmitting partner acknowledges the change.

This process is performed first for the VOD, then the pre-emphasis, the first post‑tap, and then pre-emphasis pre-tap.

The optional backplane daisy-chain topology can replace the spoke or hub switch topology. The following illustration highlights the steps required for TX Equalization for Daisy Chain Mode.

Figure 19. TX Equalization in Daisy-Chain Mode

Data transmission proceeds clockwise from link partner A, to B, to C. TX equalization includes the following steps which are identified in the figure :

  1. The receiving partner B calculates the BER for data received from transmitting partner A.
  2. The receiving partner B sends updates for TX link partner C.
  3. The receiving link partner C transmits an update to the transmitting link partner A.
  4. Transmit partner A updates its equalization settings.
  5. Transmit partner A acknowledges the change.

This procedure is repeated for the other two link partners.

Sequencer

The Sequencer (Rate change) block controls the start-up (reset, power-on) sequence of the PHY IP. It automatically selects which PCS (1G, 10GbE, or Low Latency) is required and sends requests to reconfigure the PCS. The Sequencer also performs the parallel detection function that reconfigures between the 1G and 10GbE PCS until the link is established or times out.

Auto Negotiation (AN), Clause 73

The Auto Negotiation module in the 10GBASE-KR PHY IP implements Clause 73 of the Ethernet standard. This module currently supports auto negotiation between 1GbE and 10GBASE-R data rates. Auto negotiation with XAUI is not supported. Auto negotiation is run upon power up or if the auto negotiation module is reset.

The following figures illustrate the handshaking between the Auto Negotiation, Link Training, Sequencer and Transceiver Reconfiguration Controller blocks. Reconfig controller should use lt_start_rc signal in combination with main_rc, post_rc, pre_rc, and tap_to_upd to change TX equalization settings.

Figure 20. Transition from Auto Negotiation to Link Training Mode

The Transceiver Reconfiguration Controller uses seq_start_rc in combination with the pcs_mode_rc value to initiate a change to Auto Negotiation mode or from Link Training mode to 10GBASE-KR Data mode. After TX equalization completes, this timing diagram shows the transition from Link Training mode to 10GBASE-KR Data mode and MIF streaming.

Figure 21. Transition from Link Training to Data Mode

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