6.4.8. Avalon® Memory-Mapped Interface Signals
The Avalon® memory-mapped interface is an Avalon® memory-mapped interface slave port. This interface uses word addressing and provides access to the 16-bit configuration registers of the PHY.
Use this bus to specify the register address to read from or write to. The width is:
Assert this signal to request a read operation.
Data read from the specified register. The data is valid only when the csr_waitrequest signal is deasserted. The width is:
Assert this signal to request a write operation.
Data to be written to the specified register. The data is written only when the csr_waitrequest signal is deasserted. The width is:
When asserted, indicates that the PHY is busy and not ready to accept any read or write requests.
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