V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

8.10. Interlaken PHY PLL Interface

This section describes the signals in the PLL interface.
Table 105.  PLL Interface
Signal Name Direction Description
pll_ref_clk Input

Reference clock for the PHY PLLs. Refer to the Lane rate entry in the Table 100table for required frequencies.

Custom, user-defined, data rates are now supported. However, the you must choose a lane data rate that results in standard board oscillator reference clock frequency to drive the pll_ref_clk and meet jitter requirements. Choosing a lane data rate that deviates from standard reference clock frequencies may result in custom board oscillator clock frequencies which could be unavailable or cost prohibitive.