V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

20.4.2. XCVR_REFCLK_PIN_TERMINATION

Pin Planner and Assignment Editor Name

Transceiver Dedicated Refclk Pin Termination

Description

Specifies the intended termination value for the specified refclk pin. The following 3 settings are available:

  • AC_COUPLING: Altera recommends this setting for all transceiver designs. Use it for AC coupled signals. This setting implements on-chip termination and on-chip signal biasing.
  • DC_COUPLING_ INTERNAL_100_OHMS: Used this setting when the dedicated transceiver reference clock pins are fed by a DC coupled signal whose Vcm meets the device specification. This assignment implements internal on-chip termination but not on-chip signal biasing.
  • DC_COUPLING_EXTERNAL_RESISTOR: Use this assignment when the dedicated transceiver reference clock pins are fed by a DC coupled signal. This option does not implement internal on-chip termination or signal biasing. You must implement termination and signal biasing outside of the FPGA. This assignment is recommended for compliance with the PCI Express Card Electromechanical Specification Rev. 2.0 and the HCSL IO Standard.

Options

  • AC_COUPLING
  • DC_COUPLING_INTERNAL_100_OHMS
  • DC_COUPLING_EXTERNAL_RESISTOR

Assign To

Pin - PLL refclk pin

Did you find the information on this page useful?

Characters remaining:

Feedback Message