V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

3.11. 10GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces

This section describes the 10GBASE-R PHY status, 1588, and PLL reference clock interfaces.
Table 16.  10GBASE-R Status, 1588, and PLL Reference Clock Outputs
Signal Name Direction Description
rx_block_lock Output Asserted to indicate that the block synchronizer has established synchronization.
rx_hi_ber Output Asserted by the BER monitor block to indicate a Sync Header high bit error rate greater than 10-4.
rx_recovered_clk[<n>:0] Output This is the RX clock, which is recovered from the received data stream.
pll_locked Output When asserted, indicates that the TX PLL is locked.
IEEE 1588 Precision Time Protocol
rx_latency_adj_10g [15:0] Output When you enable 1588, this signal outputs the real time latency in XGMII clock cycles (156.25 MHz) for the RX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 15 represent the number of clock cycles.
tx_latency_adj_10g [15:0] Output When you enable 1588, this signal outputs real time latency in XGMII clock cycles (156.25 MHz) for the TX PCS and PMA datapath for 10G mode. Bits 0 to 9 represent the fractional number of clock cycles. Bits 10 to 15 represent the number of clock cycles.
PLL Reference Clock
pll_ref_clk Input For Stratix IV GT devices, the TX PLL reference clock must be 644.53125 MHz. For Arria V and Stratix V devices, the TX PLL reference clock can be either 644.53125 MHz or 322.265625 MHz.

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