V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
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3.16. 10GBASE-R PHY Clocks for Stratix V Devices

The following figure illustrates clock generation and distribution in Stratix V devices.

Figure 15. Stratix V Clock Generation and Distribution

To ensure proper functioning of the PCS, the maximum PPM difference between the pll_ref_clk and xgmii_tx_clk clock inputs is 0 PPM. The FIFO in the RX PCS can compensate ±100 PPM between the RX PMA clock and xgmii_rx_clk. You should use xgmii_rx_clk to drive xgmii_tx_clk. The CDR logic recovers 257.8125 MHz clock from the incoming data.