V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

9.7. PHY for PCIe (PIPE) Output Data to the PHY MAC

This section describes the PIPE output signals. These signals are driven from the PCS to the PHY MAC. This interface is compliant to the appropriate PIPE interface specification.
Table 114.  Avalon-ST RX Inputs
Signal Name Direction Description
pipe_rxdata[[(31,16or 8)-1:0] Output

This is RX parallel data driven from the PCS to the MAC PHY. The ready latency on this interface is 0, so that the MAC must be able to accept data as soon as the PHY comes out of reset. Width is 8 or 16 for Gen1 and Gen2. Width is 32 for Gen3.

Transmission is little endian. For example, for Gen3, words are transmitted in the following order:

  • PIPE word 0: pipe_rxdata[7:0]
  • PIPE word 1: pipe_rxdata[15:8]
  • PIPE word 2: pipe_rxdata[23:16]
  • PIPE word 3: pipe_rxdata[31:24]
pipe_rxdatak[(3,2 or 1)-1:0] Output

Data and control indicator for the source data. When 0, indicates that pipe_rxdata is data, when 1, indicates that pipe_rxdata is control.

Bit[0] corresponds to byte 0. Bit[]1 corresponds to byte 1, and so on.

rx_blk_start[3:0] Output For Gen3 operation, indicates the block starting byte location in the received 32-bits data of the 130-bits block data. Data reception must start in bits [7:0] of the 32-bit data word, so that the only valid value is 4’b0001.
rx_sync_hdr[1:0] Output

For Gen3, indicates whether the 130-bit block being transmitted is a Data or Control Ordered Set Block. The following encodings are defined:

  • 2'b10: Data block
  • 2'b01: Control Ordered Set block

This valued is read when rx_blk_start = 4'b0001. Refer to “Section 4.2.2.1. Lane Level Encoding” in the PCI Express Base Specification, Rev. 3.0 for a detailed explanation of data transmission and reception using 128b/130b encoding and decoding.

pipe_rx_data_valid Output For Gen3, this signal is deasserted by the PHY to instruct the MAC to ignore pipe_rxdata for one clock cycle. A value of 1 indicates the MAC should use the data. A value of 0 indicates the MAC should not use the data.
pipe_rxvalid[<n>-1:0] Output Asserted when RX data and control are valid.
pipe_rxelecidle Output

When asserted, indicates receiver detection of an electrical idle.

For Gen2 and Gen3 data rates, the MAC uses logic to detect electrical idle entry instead of relying of this signal.

rxstatus<n>[2:0] Output

This signal encodes receive status and error codes for the receive data stream and receiver detection.The following encodings are defined:

  • 3’b000–receive data OK
  • 3’b001–1 SKP added
  • 3’b010–1 SKP removed
  • 3’b011–Receiver detected
  • 3’b100–Both 8B/10B or 128b/130b decode error and (optionally) RX disparity error
  • 3’b101–Elastic buffer overflow
  • 3’b110–Elastic buffer underflow
  • 3’b111–Receive disparity error, not used if disparity error is reported using 3’b100.
pipe_phystatus Output This signal is used to communicate completion of several PHY requests.
Figure 50. Rate Switch from Gen1 to Gen2 Timing DiagramIn the figure, Time T1 is pending characterization and <n> is the number of lanes.

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