9.7. PHY for PCIe (PIPE) Output Data to the PHY MAC
This is RX parallel data driven from the PCS to the MAC PHY. The ready latency on this interface is 0, so that the MAC must be able to accept data as soon as the PHY comes out of reset. Width is 8 or 16 for Gen1 and Gen2. Width is 32 for Gen3.
Transmission is little endian. For example, for Gen3, words are transmitted in the following order:
|pipe_rxdatak[(3,2 or 1)-1:0]||Output||
Data and control indicator for the source data. When 0, indicates that pipe_rxdata is data, when 1, indicates that pipe_rxdata is control.
Bit corresponds to byte 0. Bit1 corresponds to byte 1, and so on.
|rx_blk_start[3:0]||Output||For Gen3 operation, indicates the block starting byte location in the received 32-bits data of the 130-bits block data. Data reception must start in bits [7:0] of the 32-bit data word, so that the only valid value is 4’b0001.|
For Gen3, indicates whether the 130-bit block being transmitted is a Data or Control Ordered Set Block. The following encodings are defined:
This valued is read when rx_blk_start = 4'b0001. Refer to “Section 188.8.131.52. Lane Level Encoding” in the PCI Express Base Specification, Rev. 3.0 for a detailed explanation of data transmission and reception using 128b/130b encoding and decoding.
|pipe_rx_data_valid||Output||For Gen3, this signal is deasserted by the PHY to instruct the MAC to ignore pipe_rxdata for one clock cycle. A value of 1 indicates the MAC should use the data. A value of 0 indicates the MAC should not use the data.|
|pipe_rxvalid[<n>-1:0]||Output||Asserted when RX data and control are valid.|
When asserted, indicates receiver detection of an electrical idle.
For Gen2 and Gen3 data rates, the MAC uses logic to detect electrical idle entry instead of relying of this signal.
This signal encodes receive status and error codes for the receive data stream and receiver detection.The following encodings are defined:
|pipe_phystatus||Output||This signal is used to communicate completion of several PHY requests.|