V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

14.4. General Parameters

This section lists the parameters available on the General Options tab.
Table 226.  General and Datapath Options

Name

Range

Description

Device speed grade

3fastest–6_H6

Specifies the speed grade.

Message level for rule violations

error warning

Allows you to specify the message level, as follows:

  • error: Intel® Quartus® Prime checker will not create an instance with invalid parameters. You must change incompatible parameter selections to proceed.
  • warning: Intel® Quartus® Prime checker will allow instance creation with invalid parameters, but the instance will not compile successfully.
Datapath Options

Enable TX datapath

On/Off

When you turn this option On, the core includes the TX datapath.

Enable RX datapath

On/Off

When you turn this option On, the core includes the RX datapath.

Enable Standard PCS

On/Off

When you turn this option On, the core includes the Standard PCS.

Number of data channels

1-36

Specifies the total number of data channels in each direction.

Bonding mode

Bonded or xN

Non-bonded or x1

In Non–bonded mode, each channel is assigned a PLL.

If one PLL drives multiple channels, PLL merging is required. During compilation, the Intel® Quartus® Prime Fitter, merges all the PLLs that meet PLL merging requirements. Refer to Merging TX PLLs In Multiple Transceiver PHY Instances to observe PLL merging rules.

Select ×N to use the same clock source for up to 6 channels in a single transceiver bank or the same clock source for all the transceivers on one side of the device. ×N bonding results in reduced clock skew. You must use contiguous channels when you select ×N bonding.

For more information about the clock architecture of bonding, refer to “Transmitter Clock Network” in Transceiver Clocking in Arria V Devices in volume 2 of the Arria V Device Handbook.

Enable simplified data interface

On/Off

When you turn this option On, the data interface provides only the relevant interface to the FPGA fabric for the selected configuration. You can only use this option for static configurations.

When you turn this option Off, the data interface provides the full physical interface to the fabric. Select this option if you plan to use dynamic reconfiguration that includes changing the interface to the FPGA fabric.

Refer to “Active Bits for Each Fabric Interface Width” for guidance.

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