19. Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices
When a fractional PLL functions as the TX PLL, you must configure the Native PHY IP Core to use external PLLs. If you also want to use CMU or ATX PLLs, you must use the device-specific Transceiver PLL to instantiate them.
The MegaCore Library includes the following IP cores to instantiate external CMU and ATX PLLs:
- Stratix V Transceiver PLL
- Arria V Transceiver PLL
- Arria V GZ Transceiver PLL
Designs that dynamically reconfigure the TX PLL between the CMU PLL and fractional PLL, must also select Use external TX PLL in the Native PHY GUI and instantiate all PLLs externally as shown in the figure above. Dynamic reconfiguration is only supported for non-bonded configurations. Dynamic reconfiguration allows you to implement the following features:
- TX PLL reconfiguration between up to 5 input reference clocks
- PLL switching using the x1 clock lines within a transceiver triplet
- PLL switching using the x6 and xN clock lines when the TX channels are not in the same transceiver bank
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