V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

19. Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices

When a fractional PLL functions as the TX PLL, you must configure the Native PHY IP Core to use external PLLs. If you also want to use CMU or ATX PLLs, you must use the device-specific Transceiver PLL to instantiate them.

The MegaCore Library includes the following IP cores to instantiate external CMU and ATX PLLs:

  • Stratix V Transceiver PLL
  • Arria V Transceiver PLL
  • Arria V GZ Transceiver PLL
You instantiate the Altera Phase-Locked Loop (ALTERA_ PLL) IP Core to specify the fractional PLL and the Native PHY IP Core to specify the PMA and PCS settings. In the Native PHY GUI, select the Use external TX PLL option under the TX PLL Options heading. When you choose this option, the Native PHY includes a top-level bus, ext_pll_clk[<p>-1:0] that you can connect to the external CMU, ATX, and fractional PLLs. To achieve different TX channel data rates, you create point-to-point connections between ext_pll_clk[<p>-1:0] and the CMU, ATX, and fractional PLLs required.
Figure 107. IP Cores Required for Designs Using the Fractional PLL The following figure show the IP Cores you can instantiate to create designs that use a fractional PLL as the TX PLL. The figure also illustrates the use of Transceiver PLL to instantiate CMU and ATX PLLs. The MegaCore Library includes separate Transceiver PLL and Native PHY IP Cores for each V-Series Device Family. This figure shows logical connectivity between IP Cores and does not reflect the physical location of hardware in V-Series devices.

Designs that dynamically reconfigure the TX PLL between the CMU PLL and fractional PLL, must also select Use external TX PLL in the Native PHY GUI and instantiate all PLLs externally as shown in the figure above. Dynamic reconfiguration is only supported for non-bonded configurations. Dynamic reconfiguration allows you to implement the following features:

  • TX PLL reconfiguration between up to 5 input reference clocks
  • PLL switching using the x1 clock lines within a transceiver triplet
  • PLL switching using the x6 and xN clock lines when the TX channels are not in the same transceiver bank
Note: It is not recommended to use fractional PLL in fractional mode for transceiver applications as a TX PLL or for PLL cascading.