V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

10.4.6.5. Custom PCS

Table 146.  Custom PCS
Word Addr Bits R/W Register Name Description
0x080 [31:0] RW Lane or group number Specifies lane or group number for indirect addressing, which is used for all PCS control and status registers. For variants that stripe data across multiple lanes, this is the logical group number. For non‑bonded applications, this is the logical lane number.
0x081 [5:1] R rx_bitslipboundaryselect

out

This is an output from the bit slip word aligner which shows the number of bits slipped.

From block: Word aligner.

[0] R rx_phase_comp_fifo_error When set, indicates an RX phase compensation FIFO error.

From block: RX phase Compensation FIFO

0x082 [0] RW tx_phase_comp_fifo_error When set, indicates an TX phase compensation FIFO error.

From block: TX phase Compensation FIFO

0x083 [5:1] RW tx_bitslipboundary_select Sets the number of bits that the TX bit slipper needs to slip.

To block: Word aligner.

[0] RW tx_invpolarity When set, the TX interface inverts the polarity of the TX data.

To block: 8B/10B encoder.

0x084 0 RW rx_invpolarity When set, the RX channels inverts the polarity of the received data.

To block: 8B/10B decoder.

0x085 [3] RW rx_bitslip Every time this register transitions from 0 to 1, the RX data slips a single bit.

To block: Word aligner.

[2] RW rx_bytereversal_enable When set, enables byte reversal on the RX interface.

To block: Byte deserializer.

[1] RW rx_bitreversal_enable When set, enables bit reversal on the RX interface.

To block: Word aligner.

[0] RW rx_enapatternalign When set in manual word alignment mode, the word alignment logic begins operation when this pattern is set.

To block: Word aligner.

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