V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

11.11. Low Latency PHY Clock Interface

The following table describes reference clock for the Low Latency PHY. The input reference clock, pll_ref_clk, drives a PLL inside the PHY-layer block, and a PLL output clock, rx_clkout is used for all data, command, and status inputs and outputs.

Table 157.  Clock Signals

Signal Name

Direction

Description

tx_coreclkin[<n>-1:0]

Input

This is an optional clock to drive the write side of the TX FIFO.

rx_coreclkin[<n>-1:0]

Input

This is an optional clock to drive the read side of the RX FIFO.

pll_ref_clk

Input

Reference clock for the PHY PLLs. The frequency range is 60–700 MHz.

Did you find the information on this page useful?

Characters remaining:

Feedback Message