V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

10.4.6. Custom PHY IP Core Registers

This topic specifies the registers that you can access over the PHY management interface using word addresses and a 32‑bit embedded processor. A single address space provides access to all registers.
Note: Writing to reserved or undefined register addresses may have undefined side effects.

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