V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
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4.16. Creating a 10GBASE-KR Design

Here are the steps you must take to create a 10GBASE-KR design using this PHY.
  1. Generate the 10GBASE-KR PHY with the required parameterization.
  2. Generate a Transceiver Reconfiguration Controller with the correct number of reconfiguration interfaces based on the number of channels you are using. This controller is connected to all the transceiver channels. It implements the reconfiguration process.
  3. Generate a Transceiver Reset Controller.
  4. Create arbitration logic that prioritizes simultaneous reconfiguration requests from multiple channels. This logic should also acknowledge the channel being serviced causing the requestor to deassert its request signal.
  5. Create a state machine that controls the reconfiguration process. The state machine should:
    1. Receive the prioritized reconfiguration request from the arbiter
    2. Put the Transceiver Reconfiguration Controller into MIF streaming mode.
    3. Select the correct MIF and stream it into the appropriate channel.
    4. Wait for the reconfiguration process to end and provide status signal to arbiter.
  6. Generate one ROM for each required configuration.
  7. Create a MIF for each configuration and associate each MIF with a ROM created in Step 6. For example, create a MIF for 1G with 1588 , a MIF for 10G with 1588, and a MIF for AN/LT. AN/LT MIF is is used to reconfigure the PHY into low latency mode during AN/LT. These MIFs are the three configurations used in the MIF streaming process. The example design contains five required MIFs (1G, 10G, 1G with 1588,10G with 1588 and AN/LT). Altera recommends that you use these MIFs even if you are not using the example design.
  8. Generate a fractional PLL to create the 156.25 MHz XGMII clock from the 10G reference clock.
  9. Instantiate the PHY in your design based on the required number of channels.
  10. To complete the system, connect all the blocks.