V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents PMA Common Control and Status Registers

Table 142.  PMA Common Control and Status Registers
Word Addr Bits R/W Register Name Description
0x022 [31:0] R pma_tx_pll_is_locked Bit[P] indicates that the TX/CMU PLL (P) is locked to the input reference clock. There is typically one pma_tx_pll_is_locked bit per system.

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