V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents
Give Feedback

21.4. Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and Stratix V Devices

This section lists the PHY IP Core for PCI Express PHY (PIPE) parameters and the corresponding ALTGX megafunction parameters.
Table 357.  Comparison of ALTGX Megafunction and PHY IP Core for PCI Express PHY (PIPE) Parameters
ALTGX Parameter Name (Default Value) CI Express PHY (PIPE) Parameter Name Comments
Number of channels Number of Lanes
Channel width Deserialization factor
Subprotocol Protocol Version
Input clock frequency PLL reference clock frequency
Starting Channel Number Automatically set to 0. Intel® Quartus® Prime software handles lane assignments.
Enable low latency sync pipe_low_latency_syncronous_mode
Enable RLV with run length of pipe_run_length_violation_checking Always on
Enable electrical idle inference functionality Enable electrical idle inferencing
phy_mgmt_clk_in_mhz

For embedded reset controller to calculate delays

Train receiver CDR from pll_inclk (false) Not available in MegaWizard Interface Use assignment editor to make these assignments
TX PLL bandwidth mode (Auto)
RX CDR bandwidth mode (Auto)
Acceptable PPM threshold (±300)
Analog Power(VCCA_L/R) (Auto)
Reverse loopback option (No loopback)
Enable static equalizer control (false)
DC gain (1)
RX Vcm (0.82)
Force signal detection (Off)
Signal Detect threshold (4)
Use external receiver termination (Off)
RX term (100)
Transmitter buffer power(VCCH) (1.5)
TX Vcm (0.65)
Use external transmitter termination (Off)
TX Rterm (100)
VCO control setting (5)
Pre-emphasis 1st post tap (18) Not available in MegaWizard Interface Use assignment editor to make these assignments
Pre-tap (0)
2nd post tap (0)
DPRIO - VOD, Pre-em, Eq and EyeQ (Off)
DPRIO - Channel and TX PLL Reconfig (Off)