V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

4.14. PMA Registers

The PMA registers allow you to reset the PMA and provide status information.
Table 42.  PMA Registers - Reset and StatusThe following PMA registers allow you to reset the PMA and provide status information.
Addr Bit Access Name Description
0x22 0 RO pma_tx_pll_is_locked Indicates that the TX PLL is locked to the input reference clock.
0x44 1 RW reset_tx_digital Writing a 1 causes the internal TX digital reset signal to be asserted. You must write a 0 to clear the reset condition.
2 RW reset_rx_analog Writing a 1 causes the internal RX analog reset signal to be asserted. You must write a 0 to clear the reset condition.
3 RW reset_rx_digital Writing a 1 causes the internal RX digital reset signal to be asserted. You must write a 0 to clear the reset condition.
0x61 [31:0] RW phy_serial_loopback Writing a 1 puts the channel in serial loopback mode.
0x64 [31:0] RW pma_rx_set_locktodata When set, programs the RX CDR PLL to lock to the incoming data.
0x65 [31:0] RW pma_rx_set_locktoref When set, programs the RX clock data recovery (CDR) PLL to lock to the reference clock.
0x66 [31:0] RO pma_rx_is_lockedtodata When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode.
0x67 [31:0] RO pma_rx_is_lockedtoref When asserted, indicates that the RX CDR PLL is locked to the reference clock.
Table 43.  PMA Registers - TX and RX Serial Data Interface The following PMA registers allow you to customize the TX and RX serial data interface
Address Bit R/W Name Description
0xA8 0 RW tx_invpolarity When set to 1, the TX interface inverts the polarity of the TX data. Inverted TX data is output from the 8B/10B encoder.
1 RW rx_invpolarity When set to 1, the RX channels inverts the polarity of the received data. Inverted RX data is input to the 8B/10B decoder.
2 RW rx_bitreversal_enable When set to 1, enables bit reversal on the RX interface. The RX data is input to the word aligner.
3 RW rx_bytereversal_enable When set, enables byte reversal on the RX interface. The RX data is input to the byte deserializer.
4 RW force_electrical_idle When set to 1, forces the TX outputs to electrical idle.
0xA9 0 R rx_syncstatus When set to 1, indicates that the word aligner is synchronized to incoming data.
1 R rx_patterndetect When set to 1, indicates the 1G word aligner has detected a comma.
2 R rx_rlv When set to 1, indicates a run length violation.
3 R rx_rmfifodatainserted When set to 1, indicates the rate match FIFO inserted code group.
4 R rx_rmfifodatadeleted When set to 1, indicates that rate match FIFO deleted code group.
5 R rx_disperr When set to 1, indicates an RX 8B/10B disparity error.
6 R rx_errdetect When set to 1, indicates an RX 8B/10B error detected.

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