4.7. 10GBASE-KR PHY Arbitration Logic Requirements
The arbiter should implement the following logic. You can modify this logic based on your system requirements:
- Accept requests from either the Sequencer or Link Training block. Prioritize requests to meet system requirements. Requests should consist of the following two buses:
- Channel number—specifies the requested channel
- Mode—specifies 1G or 10G data modes or AN or LT modes for the corresponding channel
- Select a channel for reconfiguration and send an ack/busy signal to the requestor. The requestor should deassert its request signal when the ack/busy is received.
- Pass the selected channel and rate information or PMA reconfiguration information for LT to the state machine for processing.
- Wait for a done signal from the state machine indicating that the reconfiguration process is complete and it is ready to service another request.
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