V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

4.8. 10GBASE-KR PHY State Machine Logic Requirements

The state machine should implement the following logic. You can modify this logic based on your system requirements:

  1. Wait for reconfig_busy from the Transceiver Reconfiguration Controller to be deasserted and the tx_ready and rx_ready signals from the Transceiver PHY Reset Controller to be asserted. These conditions indicate that the system is ready to service a reconfiguration request.
  2. Set the appropriate channel for reconfiguration.
  3. Initiate the MIF streaming process. The state machine should also select the appropriate MIF (stored in the ROMs) to stream based on the requested mode.
  4. Wait for the reconfig_busy signal from the Transceiver Reconfiguration Controller to assert and then deassert indicating the reconfiguration process is complete.
  5. Toggle the digital resets for the reconfigured channel and wait for the link to be ready.
  6. Deassert the ack/busy signal for the selected channel. Deassertion of ack/busy indicates to the arbiter that the reconfiguration process is complete and the system is ready to service another request.