V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

17.1. Transceiver Reconfiguration Controller System Overview

This section describes the Transceiver Reconfiguration Controller’s role. You can include the embedded controller that initiates reconfiguration in your FPGA or use an embedded processor on the PCB.
Figure 88. Transceiver Reconfiguration Controller

An embedded controller programs the Transceiver Reconfiguration Controller using its Avalon-MM slave interface. The reconfig_to_xcvr and reconfig_from_xcvr buses include the Avalon-MM address, read, write, readdata, writedata, and signals that connect to features related to calibration and signal integrity.

The Transceiver Reconfiguration Controller provides two modes to dynamically reconfigure transceiver settings:

  • Register Based—In this access mode you can directly reconfigure a transceiver PHY IP core using the Transceiver Reconfiguration Controller’s reconfiguration management interface. You initiate reconfiguration using a series of Avalon-MM reads and writes to the appropriate registers of the Transceiver Reconfiguration Controller. The Transceiver Reconfiguration Controller translates the device independent commands received on the reconfiguration management interface to device dependent commands on the transceiver reconfiguration interface. For more information, refer to Changing Transceiver Settings Using Register-Based Reconfiguration.

    For more information about Avalon-MM interfaces including timing diagrams, refer to the Avalon Interface Specifications.

  • Streamer Based —This access mode allows you to either stream a MIF that contains the reconfiguration data or perform direct writes to perform reconfiguration. The streaming mode uses a memory initialization file (.mif) to stream an update to the transceiver PHY IP core. The .mif file can contain changes for many settings. For example, a single .mif file might contain changes to the PCS datapath settings, clock settings, and PLL parameters. You specify the .mif using write commands on the Avalon-MM PHY management interface. After the streaming operation is specified, the update proceeds in a single step. For more information, refer to Changing Transceiver Settings Using Streamer-Based Reconfiguration. In the direct write mode, you perform Avalon-MM reads and writes to initiate a reconfiguration of the PHY IP. For more information, refer to Direct Write Reconfiguration.

The following table shows the features that you can reconfigure or control using register-based and MIF-based access modes for Stratix V devices.

Table 318.  Reconfiguration Feature Access Modes
Feature Register-Based Streamer-Based
PMA settings, including VOD, pre-emphasis, RX equalization DC gain, RX equalization control Yes Yes
Pre-CDR and post-CDR loopback modes Yes
DFE post taps and polarity Yes
AEQ mode Yes
Eye Monitor Yes
ATX Tuning Yes Yes
Reference clock Yes Yes
TX PLL clock switching Yes
Channel interface Yes

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