V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

17.6. Transceiver Reconfiguration Controller Memory Map

Each register-based feature has its own Avalon-MM address space within the Transceiver Reconfiguration Controller.

Figure 90. Memory Map of the Transceiver Reconfiguration Controller Registers

The following table lists the address range for the Transceiver Reconfiguration Controller and the reconfiguration and signal integrity modules. The Avalon-MM interface uses byte addresses.

Table 324.  Transceiver Reconfiguration Controller Address Map
Address Link
7'h08-7'h0C PMA Analog Control Registers
7'h10-7'h14 EyeQ Registers
7'h18-7'h1C DFE Registers
7'h28-7'h2C AEQ Registers
7'h30-7'h34 ATX PLL Calibration Registers
7'h38-7'h3C Streamer Module Registers
7'h40-7'h44 PLL Reconfiguration

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