V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

7.20. Simulation Files and Example Testbench

Refer to “Running a Simulation Testbench” for a description of the directories and files that the Intel® Quartus® Prime software creates automatically when you generate your XAUI PHY IP Core.

Refer to the Intel® FPGA Wiki for an example testbench that you can use as a starting point in creating your own verification environment.