V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

12.9. Optional TX and RX Status Interface for Deterministic Latency PHY

This section describes the optional TX and RX status interface settings for the Deterministic Latency PHY IP core.

Table 175.  Serial Interface and Status Signals
Signal Name Direction Signal Name
tx_ready Output When asserted, indicates that the TX interface has exited the reset state and is ready to transmit.
rx_ready Output When asserted, indicates that the RX interface has exited the reset state and is ready to receive.
pll_locked [<p>-1:0] Output When asserted, indicates that the PLL is locked to the input reference clock.
rx_bitslipboundaryselectout [(<n>5)-1:0] Output Specifies the number of bits slipped to achieve word alignment. In 3G (10-bit) mode, the output is the number of bits slipped. If no bits were slipped, the output is 0. In 6G (20-bit) mode, the output is (19 - the number of bits slipped). If no bits were slipped, the output is 19. The default value of rx_bitslipboundaryselectout[4:0] before alignment is achieved is 5'b01111 in 3G mode and 5'b11111 in 6G mode.
Optional Status Signals
tx_bitslipboundaryselect [(<n> 5)-1:0] Input This signal is used for bit slip word alignment mode. It selects the number of bits that the TX block must slip to achieve a deterministic latency.
rx_disperr [(<n><d>/<s>)-1:0] Output When asserted, indicates that the received 10-bit code or data group has a disparity error.
rx_errdetect [(<n><d>/<s>)-1:0] Output When asserted, indicates that a received 10-bit code group has an 8B/10B code violation or disparity error.
rx_syncstatus [(<n><d>/<s>)-1:0] Output Indicates presence or absence of synchronization on the RX interface. Asserted when word aligner identifies the word alignment pattern or synchronization code groups in the received data stream. This signal is optional.
rx_is_lockedtoref [(<n>(<d>/<s>)-1:0] Output Asserted when the receiver CDR is locked to the input reference clock. This signal is asynchronous. This signal is optional.
rx_is_lockedtodata [(<n><d>/<s>)-1:0] Output When asserted, the receiver CDR is in to lock-to-data mode. When deasserted, the receiver CDR lock mode depends on the rx_locktorefclk signal level. This signal is optional.
rx_patterndetect [(<n>(<d>/<s>)-1:0] Output When asserted, indicates that the programmed word alignment pattern has been detected in the current word boundary.
rx_rlv [<n> -1:0] Output When asserted, indicates a run length violation. Asserted if the number of consecutive 1s or 0s exceeds the number specified using the MegaWizard Plug-In Manager.
rx_runningdisp [(<n>(<d>/<s>)-1:0] Output This status signal indicates the disparity of the incoming data.

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