V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

14.6.1. Phase Compensation FIFO

The phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensating for the clock phase difference between the lowspeed parallel clock and FPGA fabric interface clock.
Note: For more information refer to the Receiver Phase Compensation FIFO and Transmitter Phase Compensation FIFO sections in the Transceiver Architecture in Arria V Devices.
Table 235.  Phase Compensation FIFO Parameters

Parameter

Range

Description

TX FIFO mode

low_latency register_fifo

The following 2 modes are possible:

  • low_latency: This mode adds 3–4 cycles of latency to the TX datapath.
  • register_fifo: In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI.

RX FIFO mode

low_latency register_fifo

The following 2 modes are possible:

  • low_latency: This mode adds 2–3 cycles of latency to the TX datapath.
  • register_fifo: In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI.

Enable tx_std_pcfifo_full port

On/Off

When you turn this option On, the TX Phase compensation FIFO outputs a FIFO full status flag.

Enable tx_std_pcfifo_empty port

On/Off

When you turn this option On, the TX Phase compensation FIFO outputs a FIFO empty status flag.

Enable rx_std_pcfifo_full port

On/Off

When you turn this option On, the RX Phase compensation FIFO outputs a FIFO full status flag.

Enable rx_std_pcfifo_empty port

On/Off

When you turn this option On, the RX Phase compensation FIFO outputs a FIFO empty status flag.

Enable rx_std_rmfifo_empty port

On/Off

When you turn this option On, the rate match FIFO outputs a FIFO empty status flag. The rate match FIFO compensates for small clock frequency differences between the upstream transmitter and the local receiver clocks by inserting or removing skip (SKP) symbols or ordered sets from the interpacket gap (IPG) or idle stream.

Enable rx_std_rmfifo_full port

On/Off

When you turn this option On, the rate match FIFO outputs a FIFO full status flag.

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