9.8. PHY for PCIe (PIPE) Clocks
|pll_ref_clk||Input||This is the 100 MHz input reference clock source for the PHY TX and RX PLL. You can optionally provide a 125 MHz input reference clock by setting the PLL reference clock frequency parameter to 125 MHz as described in PHY IP Core for PCI Express General Options.|
|fixedclk||Input||A 100 MHz or 125 MHz clock used for the receiver detect circuitry. This clock can be derived from pll_ref_clk.|
Generated in the PMA and driven to the MAC PHY interface. All data and status signals are synchronous to pipe_pclk. This clock has the following frequencies:
The following table lists the pipe_pclk frequencies for all available PCS interface widths. Doubling the FPGA transceiver width haves the required frequency.
|Capability||FPGA Transceiver Width||Gen1||Gen2||Gen3|
|Gen1 only||8 bits||250 MHz||—||—|
|16 bits||125 MHz||—||—|
|Gen2 capable||16 bits||125 MHz||250 MHz||—|
|Gen3 capable||32 bits||62.5 MHz||125 MHz||250 MHz|
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