V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

9.8. PHY for PCIe (PIPE) Clocks

This section describes the clock ports.
Table 115.  Clock Ports
Signal Name Direction Description
pll_ref_clk Input This is the 100 MHz input reference clock source for the PHY TX and RX PLL. You can optionally provide a 125 MHz input reference clock by setting the PLL reference clock frequency parameter to 125 MHz as described in PHY IP Core for PCI Express General Options.
fixedclk Input A 100 MHz or 125 MHz clock used for the receiver detect circuitry. This clock can be derived from pll_ref_clk.
pipe_pclk Output

Generated in the PMA and driven to the MAC PHY interface. All data and status signals are synchronous to pipe_pclk. This clock has the following frequencies:

  • Gen1: 62.5 MHz
  • Gen2:125 MHz
  • Gen3: 250 MHz

The following table lists the pipe_pclk frequencies for all available PCS interface widths. Doubling the FPGA transceiver width haves the required frequency.

Table 116.  pipe_pclk Frequencies
Capability FPGA Transceiver Width Gen1 Gen2 Gen3
Gen1 only 8 bits 250 MHz
16 bits 125 MHz
Gen2 capable 16 bits 125 MHz 250 MHz
Gen3 capable 32 bits 62.5 MHz 125 MHz 250 MHz