V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

9.15. PHY for PCIe (PIPE) Dynamic Reconfiguration

Dynamic reconfiguration calibrates each channel to compensate for variations due to process, voltage, and temperature (PVT).

For Stratix V devices, each channel and each TX PLL have separate dynamic reconfiguration interfaces. The MegaWizard Plug-In Manager provides informational messages on the connectivity of these interfaces. The following example shows the messages for a 8-channel PHY IP Core for PCI Express (PIPE).

Although you must initially create a separate reconfiguration interface for each channel and TX PLL in your design, when the Intel® Quartus® Prime software compiles your design, it reduces the total number of reconfiguration interfaces by merging reconfiguration interfaces. The synthesized design typically includes a reconfiguration interface for at least three channels because the three channels within each transceiver triplet share a single physical Avalon-MM slave interface which connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you cannot connect the three channels that share this single physical Avalon-MM interface to different Transceiver Reconfiguration Controllers. Doing so causes a Fitter error. For more information, refer to“Transceiver Reconfiguration Controller to PHY IP Connectivity”.

Informational Messages for the Transceiver Reconfiguration Interface

PHY IP will require 9 reconfiguration interfaces for connection to the external reconfiguration controller.
Reconfiguration interface offsets 0-7 are connected to the transceiver channels.
Reconfiguration interface offset 8 is connected to the transmit PLL.

The reconfiguration interface uses the Avalon-MM PHY Management interface clock.

Table 121.  Reconfiguration Interface Signals
Signal Name Direction Description
reconfig_to_xcvr [<r>70-1:0] Input Reconfiguration signals from the Transceiver Reconfiguration Controller. <r> grows linearly with the number of reconfiguration interfaces.
reconfig_from_xcvr [<r>46-1:0] Output Reconfiguration signals to the Transceiver Reconfiguration Controller. <r> grows linearly with the number of reconfiguration interfaces.

Did you find the information on this page useful?

Characters remaining:

Feedback Message