V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

2.3.1. Specifying Parameters

To specify IP core parameters, follow these steps:
  1. Create a Intel® Quartus® Prime project using the New Project Wizard available from the File menu.
  2. In the Intel® Quartus® Prime software, launch the IP Catalog.
  3. You can select the IP core for your protocol implementation from the IP Catalog.
  4. Specify the parameters on the Parameter Settings pages. For detailed explanations of these parameters, refer to the "Parameter Settings" chapter in this document or the "Documentation" button in the MegaWizard parameter editor.
    Note: Some IP cores provide preset parameters for specific applications. If you wish to use preset parameters, click the arrow to expand the Presets list, select the desired preset, and then click Apply. To modify preset settings, in a text editor modify the <installation directory>/ip/altera/ alt_mem_if_interfaces/alt_mem_if_<memory_protocol>_emif/ alt_mem_if_<memory_protocol>_mem_model.qprs file.
  5. If the IP core provides a simulation model, specify appropriate options in the wizard to generate a simulation model.
    • Altera IP supports a variety of simulation models, including simulation‑specific IP functional simulation models and encrypted RTL models, and plain text RTL models. These are all cycle‑accurate models. The models allow for fast functional simulation of your IP core instance using industry‑standard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is generated, and you can simulate that model.
    • For more information about functional simulation models for Altera IP cores, refer to Simulating Altera Designs in volume 3 of the Intel® Quartus® Prime Handbook.
    Use the simulation models only for simulation and not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.
  6. If the parameter editor includes EDA and Summary tabs, follow these steps:
    1. Some third-party synthesis tools can use a netlist that contains the structure of an IP core but no detailed logic to optimize timing and performance of the design containing it. To use this feature if your synthesis tool and IP core support it, turn on Generate netlist.
    2. On the Summary tab, if available, select the files you want to generate. A gray checkmark indicates a file that is automatically generated. All other files are optional.
      Note: If file selection is supported for your IP core, after you generate the core, a generation report (<variation name>.html)appears in your project directory. This file contains information about the generated files.
  7. Click the Finish button, the parameter editor generates the top-level HDL code for your IP core, and a simulation directory which includes files for simulation.
    Note: The Finish button may be unavailable until all parameterization errors listed in the messages window are corrected.
  8. Click Yes if you are prompted to add the Intel® Quartus® Prime IP File (.qip) to the current Intel® Quartus® Prime project. You can also turn on Automatically add Intel® Quartus® Prime IP Files to all projects.

You can now integrate your custom IP core instance in your design, simulate, and compile. While integrating your IP core instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.

For some IP cores, the generation process also creates complete example designs. An example design for hardware testing is located in the < variation_name > _example_design/example_project/ directory. An example design for RTL simulation is located in the < variation_name > _example_design/simulation/ directory.

Note: For information about the Intel® Quartus® Prime software, including virtual pins, refer to Intel® Quartus® Prime Help.

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