V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

9.5. PHY for PCIe (PIPE) Interfaces

This section describes interfaces of the PHY IP Core for PCI Express (PIPE).

The following figure illustrates the top-level pinout of the PHY IP Core for PCI Express PHY. The port descriptions use the following variables to represent parameters:

  • <n>—The number of lanes
  • <d>—The total deserialization factor from the input pin to the PHY MAC interface.
  • <s>—The symbols size.
  • <r>—The width of the reconfiguration interface; <r> is automatically calculated based on the selected configuration.
Figure 49. Top-Level Signals of the PHY IP Core for PCI Express
Note: The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box. The interface type and name are used in the _hw.tcl file. If you turn on Show signals, the block diagram displays all top-level signal names.

For more information about _hw.tcl files, refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Intel® Quartus® Prime Handbook.

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