9.5. PHY for PCIe (PIPE) Interfaces
The following figure illustrates the top-level pinout of the PHY IP Core for PCI Express PHY. The port descriptions use the following variables to represent parameters:
- <n>—The number of lanes
- <d>—The total deserialization factor from the input pin to the PHY MAC interface.
- <s>—The symbols size.
- <r>—The width of the reconfiguration interface; <r> is automatically calculated based on the selected configuration.
For more information about _hw.tcl files, refer to refer to the Component Interface Tcl Reference chapter in volume 1 of the Intel® Quartus® Prime Handbook.
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