V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

20.3.2.2. master_ch_number

Pin Planner and Assignment Editor Name

Parameter (Assignment Editor Only)

Description

For the PHY IP Core for PCI Express (PIPE), specifies the channel number of the channel acting as the master channel for a single transceiver bank or 2 adjacent banks. This setting allows you to override the default master channel assignment for the PCS and PMA. The master channel must use a TX PLL that is in the same transceiver bank. Available for Gen1, Gen2, and Gen3 variants.
Example: set_parameter -name master_ch_number 4 -to
"<design>.pcie_i|altera_xcvr_pipe:<design>_inst|
sv_xcvr_pipe_nr:pipe_nr_inst|sv_xcvr_pipe_native:
transceiver_core"

Options

1, 4

Assign To

Include in .qsf file

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