V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

8.7. Interlaken PHY Avalon-ST TX Interface

This section lists the signals in the Avalon-ST TX interface.
Table 102.  Avalon-ST TX Signals
Signal Name Direction Description
tx_parallel_data<n>[63:0] Input Avalon-ST data bus driven from the FPGA fabric to the TX PCS. This input should be synchronized to the tx_coreclkin clock domain.
tx_parallel_data<n>[64] Input

Indicates whether tx_parallel_data<n>[63:0] represents control or data. When deasserted, tx_parallel_data<n>[63:0] is a data word. When asserted, tx_parallel_data<n>[63:0] is a control word.

The value of header synchronization bits[65:64] of the Interlaken word identify whether bits[63:0] are a Framing Layer Control/Burst/IDLE Control Word or a data word. The MAC must gray encode the header synchronization bits. The value 2'b10 indicating Burst/IDLE Control Word must be gray encoded to the value 1'b1 for tx_parallel_data<n>[64]. The value 2'b01 indicating data word must be gray encoded to the value 1'b0 for tx_parallel_data<n>[64]. You can also tie header synchronization bit[65] to tx_parallel_data[64] directly.

tx_parallel_data<n>[65] Input

When asserted, indicates that tx_parallel_data<n>[63:0] is valid and is ready to be written into the TX FIFO. When deasserted, indicates that tx_parallel_data<n>[63:0] is invalid and is not written into the TX FIFO. This signal is the data valid or write enable port of the TX FIFO. This input must be synchronized to the tx_coreclkin clock domain.

The Interlaken MAC should gate tx_parallel_data<n>[65] based on tx_datain_bp<n>. Or, you can tie tx_datain_bp<n> directly to tx_parallel_data<n>[65]. For Quartus II releases before 12.0, you must pre-fill the transmit FIFO so this pin must be 1'b1 when tx_ready is asserted, but before tx_sync_done is asserted to insert the pre-fill pattern. Do not use valid data to pre-fill the transmit FIFO. Use the following Verilog HDL assignment for Quartus II releases prior to 12.0:

assign tx_parallel_data[65] = (!tx_sync_done)?1'b1:tx_datain_bp[0];

tx_ready Output When asserted, indicates that the TX interface has exited the reset state and is ready for service. The tx_ready latency for the TX interface is 0. A 0 latency means that the TX FIFO can accept data on the same clock cycle that tx_ready is asserted. This output is synchronous to the phy_mgmt_clk clock domain. The Interlaken MAC must wait for tx_ready before initiating data transfer (pre-fill pattern or valid user data) on any lanes. The TX FIFO only captures input data from the Interlaken MAC when tx_ready and tx_parallel_data[65] are both asserted. The beginning of the pre-fill stage is marked by the assertion of tx_ready, before tx_sync_done is asserted. The pre-fill stage should terminate when tx_ready is high and tx_sync_done changes from Logic 0 to Logic 1 state. At this point, TX synchronization is complete and valid TX data insertion can begin. TX synchronization is not required for single-lane variants. Use the following Verilog HDL assignment is for Quartus versions earlier than 12.0:

assign tx_parallel_data[65] = (!tx_sync_done)?1'b1:tx_datain_bp[0];

tx_datain_bp<n> Output

When asserted, indicates that Interlaken TX lane <n> interface is ready to receive data for transmission. In multi‑lane configurations, the tx_datain_bp<n> signals must be logically Ored. The latency on this Avalon-ST interface is 0 cycles. The Interlaken MAC must only drive valid user data on tx_parallel_data<n>[64] and tx_parallel_data<n>[63:0] data bus as soon as tx_ready<n> and tx_sync_done are both asserted. The tx_datain_bp<n> signal is connected to the partial empty threshold of the TX FIFO, so that when tx_datain_bp<n> is deasserted the TX FIFO back pressures the Interlaken MAC. Stop sending TX data to the PHY when this signal is deasserted.

The Interlaken MAC can continue driving data to the TX FIFO when tx_datain_bp<n> is asserted. The Interlaken MAC should gate tx_parallel_data<n>[65], which operates as a data_valid signal, based on tx_datain_bp<n> . This output is synchronous to the tx_coreclkin clock domain. Or, you can also tie tx_datain_bp<n> directly to tx_parallel_data<n>[65] . For Quartus II releases prior to 12.0, you must pre‑fill the TX FIFO before tx_sync_done can be asserted. Do not use valid data to pre‑fill the TX FIFO. Use the following Verilog HDL assignment for Quartus II releases prior to 12.0:

assign tx_parallel_data[65] = (!tx_sync_done)?1'b1:tx_datain_bp[0];

tx_clkout Output For single lane Interlaken links, tx_user_clkout is available when you do not create the optional tx_coreclkin . For Interlaken links with more than 1 lane, tx_coreclkin is required and tx_user_clkout cannot be used. tx_coreclkin must have a minimum frequency of the lane data rate divided by 67. The frequency range for tx_coreclkin is (data rate/40) - (data rate/67). For best results, Altera recommends that tx_coreclkin = (data rate/40).
tx_user_clkout Output For single lane Interlaken links, tx_user_clkout is available when you do not create the optional tx_coreclkin. For Interlaken links with more than 1 lane, tx_coreclkin is required and tx_user_clkout cannot be used. You can use a minimum frequency of lane datarate divided by 67 for tx_coreclkin, although Altera recommends that tx_coreclkin frequency of the lane data rate divided by 40 for best performance.
pll_locked Output In multilane Interlaken designs, this signal is the bitwise AND of the individual lane pll_locked signals. This output is synchronous to the phy_mgmt_clk clock domain.
tx_sync_done Output

When asserted, indicates that all tx_parallel_data lanes are synchronized and ready for valid user data traffic. The Interlaken MAC must wait for this signal to be asserted before initiating valid user data transfers on any lane. This output is synchronous to the tx_coreclkin clock domain. For consistent tx_sync_done performance, Altera recommends using tx_coreclkin and rx_coreclkin frequency of lane (data rate/40).

You must invoke a hard reset using mgmt_rst_reset and phy_mgmt_clk_reset to initiate the synchronization sequence on the TX lanes.

After tx_sync_done is asserted, you must never allow the TX FIFO to underflow, doing so requires you to hard reset to the Interlaken PHY IP Core.

For Quartus versions prior to 12.0, you must pre‑fill the TX FIFO before tx_sync_done can be asserted. Use the following Verilog HDL assignment for Quartus II releases prior to 12.0:

assign tx_parallel_data[65] = (!tx_sync_done)?1'b1:tx_datain_bp[0];

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