V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

17.5.3. Reconfiguration Management Interface

This section describes the reconfiguration management interface.

The reconfiguration management interface is an Avalon-MM slave interface. You can use an embedded controller to drive this interface. Alternatively, you can use a finite state machine to control all Avalon-MM reads and writes to the Transceiver Reconfiguration Controller. This interface provides access to the Transceiver Reconfiguration Controller’s Avalon-MM registers.

For more information about the Avalon-MM protocol, including timing diagrams, refer to the Avalon Interface Specifications.

Table 323.  Reconfiguration Management Interface
Signal Name Direction Description
mgmt_clk_clk Input Avalon-MM clock input. The frequency range for the mgmt_clk_clk is 100-125 MHz for Stratix V and Arria V GZ devices. It is 75-125 MHz for Arria V devices. For Cyclone V devices, the frequency range is 75-125MHz if the Cyclone V Hard IP for PCI Express IP Core is not enabled. When the Hard IP for PCI Express is enabled, the frequency range is 75-100 MHz. Falling outside of the required frequency range may reduce the accuracy of the calibration functions.
If your design includes the following components:
  • The Stratix V Hard IP for PCI Express with CvP enabled
  • Any additional transceiver PHY connected to the same Transceiver Reconfiguration Controller
then you must connect the PLL reference clock which is called refclk in the Stratix V Hard IP for PCI Express IP Core to the mgmt_clk_clk signal of the Transceiver Reconfiguration Controller and the additional transceiver PHY. In addition, if your design includes more than one Transceiver Reconfiguration Controllers on the same side of the FPGA, they all must share the mgmt_clk_clk signal.
Note: The frequency range depends on the device speed grade. Slower speed grade variants of Stratix V and Arria V GZ devices may require a 100 MHz reconfiguration clock to close timing.
mgmt_rst_reset Input

This signal resets the Transceiver Reconfiguration Controller. This signal is active high and level sensitive.

If the Transceiver Reconfiguration Controller IP Core connects to an Interlaken PHY IP Core, the Reconfiguration Controller IP Core mgmt_rst_reset must be simultaneously asserted with phy_mgmt_clk_reset to bring the Frame Generators in the link into alignment. Failure to meet to this requirement will result in excessive transmit lane-to-lane skew in the Interlaken link.

reconfig_mgmt_address[6:0] Input Avalon-MM address.
reconfig_mgmt_writedata[31:0] Input Input data.
reconfig_mgmt_readdata[31:0] Output Output data.
reconfig_mgmt_write Input Write signal. Active high.
reconfig_mgmt_read Input Read signal. Active high.

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