V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

8.9. Interlaken PHY TX and RX Serial Interface

This section describes the signals in the chip-to-chip serial interface.
Table 104.  Serial Interface
Signal Name Direction Description
tx_serial_data Output Differential high speed serial output data using the PCML I/O standard. Clock is embedded in the serial data stream.
rx_serial_data Input Differential high speed serial input data using the PCML I/O standard. Clock is recovered from the serial data stream.

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