V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

4.15. PCS Registers

Table 44.   PCS RegistersThese registers provide PCS status information.
Addr Bit Access Name Description
0x80 31:0 RW Indirect_addr Because the PHY implements a single channel, this register must remain at the default value of 0 to specify logical channel 0.
0x81 2 RW RCLR_ERRBLK_CNT Error Block Counter clear register. When set to 1, clears the RCLR_ERRBLK_CNT register. When set to 0, normal operation continues.
3 RW RCLR_BER_COUNT BER Counter clear register. When set to 1, clears the RCLR_BER_COUNT register. When set to 0, normal operation continues.
0x82 1 RO HI_BER High BER status. When set to 1, the PCS is reporting a high BER. When set to 0, the PCS is not reporting a high BER.
2 RO BLOCK_LOCK Block lock status. When set to 1, the PCS is locked to received blocks. When set to 0, the PCS is not locked to received blocks.
3 RO TX_FULL When set to 1, the TX_FIFO is full.
4 RO RX_FULL When set to 1, the RX_FIFO is full.
5 RO RX_SYNC_HEAD_ERROR When set to 1, indicates an RX synchronization error.
6 RO RX_SCRAMBLER_ERROR When set to 1, indicates an RX scrambler error.
7 RO Rx_DATA_READY When set to 1, indicates the PHY is ready to receive data.
Table 45.   Pattern Generator Registers1G/10Gbps Ethernet PHY IP core supports the 10G PCS Pattern Generator.

Offset

Bits

R/W

Name

Description

0x12D

[15:0]

R/W

Seed A for PRP

Bits [15:0] of seed A for the pseudo-random pattern.

0x12E

[15:0]

Bits [31:16] of seed A for the pseudo-random pattern.

0x12F

[15:0]

Bits [47:21] of seed A for the pseudo-random pattern.

0x130

[9:0]

Bits [57:48] of seed A for the pseudo-random pattern.

0x131

[15:0]

R/W

Seed B for PRP

Bits [15:0] of seed B for the pseudo-random pattern.

0x132

[15:0]

Bits [31:16] of seed B for the pseudo-random pattern.

0x133

[15:0]

Bits [47:32] of seed B for the pseudo-random pattern.

0x134

[9:0]

Bits [57:48] of seed B for the pseudo-random pattern.

0x135

[15:12]

R/W

Square Wave Pattern

Specifies the number of consecutive 1s and 0s. The following values are available: 1, 4, 5, 6, 8, and 10.

[10]

R/W

TX PRBS 7 Enable

Enables the PRBS-7 polynomial in the transmitter.

[8]

R/W

TX PRBS 23 Enable

Enables the PRBS-23 polynomial in the transmitter.

[6]

R/W

TX PRBS 9 Enable

Enables the PRBS-9 polynomial in the transmitter.

[4]

R/W

TX PRBS 31 Enable

Enables the PRBS-31 Polynomial in the transmitter.

[3]

R/W

TX Test Enable

Enables the pattern generator in the transmitter.

[1]

R/W

TX Test Pattern Select

Selects between the square wave or pseudo-random pattern generator. The following encodings are defined:

  • 1’b1: Square wave
  • 1’b0: Pseudo-random pattern or PRBS

[0]

R/W

Data Pattern Select
Selects the data pattern for the pseudo-random pattern. The following encodings are defined:
  • 1’b1: Two Local Faults. Two, 32-bit ordered sets are XORd with the pseudo-random pattern.
  • 1’b0: All 0’s

0x137

[2]

R/W

TX PRBS Clock Enable

Enables the transmitter PRBS clock.

[1]

R/W

TX Square Wave Clock Enable

Enables the square wave clock.

0x15E

[14]

R/W

RX PRBS 7 Enable

Enables the PRBS-7 polynomial in the receiver.

[13]

R/W

RX PRBS 23 Enable

Enables the PRBS-23 polynomial in the receiver.

[12]

R/W

RX PRBS 9 Enable

Enables the PRBS-9 polynomial in the receiver.

[11]

R/W

RX PRBS 31 Enable

Enables the PRBS-31 polynomial in the receiver.

[10]

R/W

RX Test Enable

Enables the PRBS pattern verifier in the receiver.

0x164

[10]

R/W

RX PRBS Clock Enable

Enables the receiver PRBS Clock.

0x169

[0]

R/W

RX Test Pattern Select

Selects between a square wave or pseudo-random pattern. The following encodings are defined:

  • 1’b1: Square wave
  • 1’b0: Pseudo-random pattern or PRBS

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