V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

3.10. 10GBASE-R PHY Data Interfaces

This section describes the 10GBASE-R PHY data interfaces.

The TX signals are driven from the MAC to the PCS. The RX signals are driven from the PCS to the MAC.

Table 13.  SDR XGMII TX Inputs
Signal Name Direction Description
XGMII TX Interface
xgmii_tx_dc_[<n>71:0] Input Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of data and 1 bit of control.
  • Lane 0-[7:0]/[8]
  • Lane 1-[16:9]/[17]
  • Lane 2-[25:18]/[26]
  • Lane 3-[34:27]/[35]
  • Lane 4-[43:36]/[44]
  • Lane 5-[52:45]/[53]
  • Lane 6-[61:54]/[62]
  • Lane 7-[70:63]/[71]
Refer toTable 14 for the mapping of the xgmii_tx_dc data and control to the xgmii_sdr_data and xgmii_sdr_ctrl signals.
tx_ready Output Asserted when the TX channel is ready to transmit data. Because the readyLatency on this Avalon-ST interface is 0, the MAC may drive tx_ready as soon as it comes out of reset.
xgmii_tx_clk Input The XGMII TX clock which runs at 156.25 MHz. Connect xgmii_tx_clk to xgmii_rx_clk to guarantee this clock is within 150 ppm of the transceiver reference clock.
XGMII RX Interface
xgmii_rx_dc_<n>[71:0] Output Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of data and 1 bit of control.
  • Lane 0-[7:0]/[8]
  • Lane 1-[16:9]/[17]
  • Lane 2-[25:18]/[26]
  • Lane 3-[34:27]/[35]
  • Lane 4-[43:36]/[44]
  • Lane 5-[52:45]/[53]
  • Lane 6-[61:54]/[62]
  • Lane 7-[70:63]/[71]
Refer toTable 15 for the mapping of the xgmii_rx_dc data and control to the xgmii_sdr_data and xgmii_sdr_ctrl signals.
rx_ready Output Asserted when the RX reset is complete.
rx_data_ready [<n>-1:0] Output When asserted, indicates that the PCS is sending data to the MAC. Because the readyLatency on this Avalon-ST interface is 0, the MAC must be ready to receive data whenever this signal is asserted. After rx_ready is asserted indicating the exit from the reset state, the MAC should store xgmii_rx_dc_<n>[71:0] in each cycle where rx_data_ready<n> is asserted.
xgmii_rx_clk Output This clock is generated by the same reference clock that is used to generate the transceiver clock. Its frequency is 156.25 MHz. Use this clock for the MAC interface to minimize the size of the FIFO between the MAC and SDR XGMII RX interface.
rx_coreclkin Input When you turn on Create rx_coreclkin port, this signal is available as a 156.25 MHz clock input port to drive the RX datapath interface (RX read FIFO).
Serial Interface
rx_serial_data_<n> Input Differential high speed serial input data using the PCML I/O standard. The clock is recovered from the serial data stream.
tx_serial_data_<n> Output Differential high speed serial input data using the PCML I/O standard. The clock is embedded from the serial data stream.
Table 14.  Mapping from XGMII TX Bus to XGMII SDR Bus
Signal Name XGMII Signal Name Description
xgmii_tx_dc_[7:0] xgmii_sdr_data[7:0] Lane 0 data
xgmii_tx_dc_[8] xgmii_sdr_ctrl[0] Lane 0 control
xgmii_tx_dc_[16:9] xgmii_sdr_data[15:8] Lane 1 data
xgmii_tx_dc_[17] xgmii_sdr_ctrl[1] Lane 1 control
xgmii_tx_dc_[25:18] xgmii_sdr_data[23:16] Lane 2 data
xgmii_tx_dc_[26] xgmii_sdr_ctrl[2] Lane 2 control
xgmii_tx_dc_[34:27] xgmii_sdr_data[31:24] Lane 3 data
xgmii_tx_dc_[35] xgmii_sdr_ctrl[3] Lane 3 control
xgmii_tx_dc_[43:36] xgmii_sdr_data[39:32] Lane 4 data
xgmii_tx_dc_[44] xgmii_sdr_ctrl[4] Lane 4 control
xgmii_tx_dc_[52:45] xgmii_sdr_data[47:40] Lane 5 data
xgmii_tx_dc_[53] xgmii_sdr_ctrl[5] Lane 5 control
xgmii_tx_dc_[61:54] xgmii_sdr_data[55:48] Lane 6 data
xgmii_tx_dc_[62] xgmii_sdr_ctrl[6] Lane 6 control
xgmii_tx_dc_[70:63] xgmii_sdr_data[63:56] Lane 7 data
xgmii_tx_dc_[71] xgmii_sdr_ctrl[7] Lane 7 control
Table 15.  Mapping from XGMII RX Bus to the XGMII SDR Bus
Signal Name XGMII Signal Name Description
xgmii_rx_dc_[7:0] xgmii_sdr_data[7:0] Lane 0 data
xgmii_rx_dc_[8] xgmii_sdr_ctrl[0] Lane 0 control
xgmii_rx_dc_[16:9] xgmii_sdr_data[15:8] Lane 1 data
xgmii_rx_dc_[17] xgmii_sdr_ctrl[1] Lane 1 control
xgmii_rx_dc_[25:18] xgmii_sdr_data[23:16] Lane 2 data
xgmii_rx_dc_[26] xgmii_sdr_ctrl[2] Lane 2 control
xgmii_rx_dc_[34:27] xgmii_sdr_data[31:24] Lane 3 data
xgmii_rx_dc_[35] xgmii_sdr_ctrl[3] Lane 3 control
xgmii_rx_dc_[43:36] xgmii_sdr_data[39:32] Lane 4 data
xgmii_rx_dc_[44] xgmii_sdr_ctrl[4] Lane 4 control
xgmii_rx_dc_[52:45] xgmii_sdr_data[47:40] Lane 5 data
xgmii_rx_dc_[53] xgmii_sdr_ctrl[5] Lane 5 control
xgmii_rx_dc_[61:54] xgmii_sdr_data[55:48] Lane 6 data
xgmii_rx_dc_[62] xgmii_sdr_ctrl[6] Lane 6 control
xgmii_rx_dc_[70:63] xgmii_sdr_data[63:56] Lane 7 data
xgmii_rx_dc_[71] xgmii_sdr_ctrl[7] Lane 7 control

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