V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

14.7.1. Common Interface Ports

This section describes the common interface ports for the IP core.

Common interface consists of reset, clock signals, serial interface ports, control and status ports, parallel data ports, PMA ports and reconfig interface ports.

Figure 75. Common Interface Ports
Table 243.  Native PHY Common Interfaces 

Name

Direction

Description

Clock Inputs and Output Signals
tx_pll_refclk[<r>-1:0]

Input

The reference clock input to the TX PLL.

tx_pma_clkout[<n>-1:0]

Output

TX parallel clock output from PMA. This clock is only available in PMA direct mode.

rx_pma_clkout[<n>-1:0]

Output

RX parallel clock (recovered clock) output from PMA

rx_cdr_refclk[<n>-1:0]

Input

Input reference clock for the RX PFD circuit.

ext_pll_clk [ <p> -1:0]

Input

This optional signal is created when you select the Use external TX PLL option. If you instantiate a fractional PLL which is external to the Native PHY IP, then connect the output clock of this PLL to ext_pll_clk.

Resets
pll_powerdown[<p>-1:0]

Input

When asserted, resets the TX PLL. Active high, edge sensitive reset signal. By default, the Arria V Native Transceiver PHY IP Core creates a separate pll_powerdown signal for each logical PLL. However, the Fitter may merge the PLLs if they are in the same transceiver bank. PLLs can only be merged if their pll_powerdown signals are driven from the same source. If the PLLs are in separate transceiver banks, you can choose to drive the pll_powerdown signals separately.
tx_analogreset[<n>-1:0]

Input

When asserted, resets for TX PMA, TX clock generation block, and serializer. Active high, edge sensitive reset signal.

Note: For Arria V devices, while compiling a multi-channel transceiver design, you will see a compile warning (12020) in Intel® Quartus® Prime software related to the signal width of tx_analogreset. You can safely ignore this warning. Also, per-channel TX analog reset is not supported in Intel® Quartus® Prime software. Channel 0 TX analog resets all the transceiver channels.
tx_digitalreset[<n>-1:0]

Input

When asserted, resets the digital components of the TX datapath. Active high, edge sensitive, asynchronous reset signal. If your design includes bonded TX PCS channels, refer to Timing Constraints for Reset Signals when Using Bonded PCS Channels for a SDC constraint you must include in your design.

rx_analogreset[<n>-1:0]

Input

When asserted, resets the RX CDR, deserializer. Active high, edge sensitive, asynchronous reset signal.

rx_digitalreset[<n>-1:0]

Input

When asserted, resets the digital components of the RX datapath. Active high, edge sensitive, asynchronous reset signal.

Parallel data ports
tx_pma_parallel_data[79:0]

Input

TX parallel data for the PMA Direct datapath. Driven directly from the FPGA fabric to the PMA. Not used when you enable the Standard PCS datapath.

rx_pma_parallel_data[79:0]

Output

RX PMA parallel data driven from the PMA to the FPGA fabric. Not used when you enable the Standard PCS datapath.

tx_parallel_data[43:0]

Input

PCS TX parallel data representing 4, 11-bit words. Used when you enable the Standard datapath. Refer to Table 244for bit definitions. Refer to Table 245 various parameterizations.

rx_parallel_data[63:0]

Output

PCS RX parallel data, representing 4, 16-bit words. Used when you enable the Standard datapath. Refer to Table 246 for bit definitions. Refer to Table 247 for various parameterizations.

TX and RX serial ports
tx_serial_data[<n>-1:0]

Output

TX differential serial output data.

rx_serial_data[<n>-1:0]

Input

RX differential serial output data.

Control and Status ports
rx_seriallpbken[<n>-1:0]

Input

When asserted, the transceiver enters serial loopback mode. Loopback drives serial TX data to the RX interface.

rx_set_locktodata[<n>-1:0]

Input

When asserted, programs the RX CDR to manual lock to data mode in which you control the reset sequence using the rx_set_locktoref and rx_set_locktodata. Refer to “Transceiver Reset Sequence” in Transceiver Reset Control in Arria V Devices for more information about manual control of the reset sequence.

rx_set_locktoref[<n>-1:0]

Input

When asserted, programs the RX CDR to manual lock to reference mode in which you control the reset sequence using the rx_set_locktoref and rx_set_locktodata. Refer to Refer to “Transceiver Reset Sequence” in Transceiver Reset Control in Arria V Devices for more information about manual control of the reset sequence.

pll_locked[<p>-1:0]

Output

When asserted, indicates that the PLL is locked to the input reference clock.

rx_is_lockedtodata[<n>-1:0]

Output

When asserted, the CDR is locked to the incoming data.

rx_is_lockedtoref[<n>-1:0]

Output

When asserted, the CDR is locked to the incoming reference clock.

rx_clkslip[<n>-1:0]

Input

When you turn this signal on, the deserializer performs a clock slip operation to achieve word alignment. The clock slip operation alternates between skipping 1 serial bit and pausing the serial clock for 2 cycles to achieve word alignment. As a result, the period of the parallel clock can be extended by 2 unit intervals (UI) during the clock slip operation. This is an optional control input signal.
Reconfig Interface Ports
reconfig_to_xcvr [(<n>70-1):0]

Input

Reconfiguration signals from the Transceiver Reconfiguration Controller. <n> grows linearly with the number of reconfiguration interfaces.

reconfig_from_xcvr [(<n>46-1):0]

Output

Reconfiguration signals to the Transceiver Reconfiguration Controller. <n> grows linearly with the number of reconfiguration interfaces.

tx_cal_busy[<n>-1:0]

Output

When asserted, indicates that the initial TX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP. You must hold the channel in reset until calibration completes.
rx_cal_busy[<n>-1:0]

Output

When asserted, indicates that the initial RX calibration is in progress. It is also asserted if reconfiguration controller is reset. It will not be asserted if you manually re-trigger the calibration IP.

Table 244.  Signal Definitions for tx_parallel_data with and without 8B/10B EncodingThe following table shows the signals within tx_parallel_data that correspond to data, control, and status signals.
TX Data Word Description
Signal Definitions with 8B/10B Enabled
tx_parallel_data[7:0] TX data bus
tx_parallel_data[8] TX data control character
tx_parallel_data[9] Force disparity, validates disparity field.
tx_parallel_data[10] Specifies the current disparity as follows:
  • 1'b0 = positive
  • 1'b1 = negative
Signal Definitions with 8B/10B Disabled
tx_parallel_data[9:0] TX data bus
tx_parallel_data[10] Unused
Table 245.  Location of Valid Data Words for tx_parallel_data for Various FPGA Fabric to PCS Parameterizations The following table shows the valid 11-bit data words with and without the byte deserializer for single- and double-word FPGA fabric to PCS interface widths.
Configuration Bus Used Bits
Single word data bus, byte deserializer disabled [10:0] (word 0)
Single word data bus, byte serializer enabled [32:22], [10:0] (words 0 and 2)
Double word data base, bye serializer disabled [21:0] (words 0 and 1)
Double word data base, bye serializer disabled [43:0] (words 0-3)
Table 246.  Signal Definitions for rx_parallel_data with and without 8B/10B EncodingThis table shows the signals within rx_parallel_data that correspond to data, control, and status signals.
RX Data Word Description
Signal Definitions with 8B/10B Enabled
rx_parallel_data[7:0] RX data bus
rx_parallel_data[8] RX data control character
rx_parallel_data[9] Error detect
rx_parallel_data[10] Word alignment / synchronization status
rx_parallel_data[11] Disparity error
rx_parallel_data[12] Pattern detect
rx_parallel_data[14:13] The following encodings are defined:
  • 2’b00: Normal data
  • 2’b01: Deletion
  • 2’b10: Insertion
  • 2’b11: Underflow
rx_parallel_data[15] Running disparity value
Signal Definitions with 8B/10B Disabled
rx_parallel_data[9:0] RX data bus
rx_parallel_data[10] Word alignment / synchronization status
rx_parallel_data[11] Disparity error
rx_parallel_data[12] Pattern detect
rx_parallel_data[14:13] The following encodings are defined:
  • 2’b00: Normal data
  • 2’b01: Deletion
  • 2’b10: Insertion (or Underflow with 9’h1FE or 9’h1F7)
  • 2’b11: Overflow
rx_parallel_data[15] Running disparity value
Table 247.  Location of Valid Data Words for rx_parallel_data for Various FPGA Fabric to PCS Parameterizations The following table shows the valid 16-bit data words with and without the byte deserializer for single- and double-word FPGA fabric to PCS interface widths.
Configuration Bus Used Bits
Single word data bus, byte deserializer disabled [15:0] (word 0)
Single word data bus, byte serializer enabled [47:32], [15:0] (words 0 and 2)
Double word data base, bye serializer disabled [31:0] (words 0 and 1)
Double word data base, bye serializer disabled [63:0] (words 0-3)

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