12.4. Deterministic Latency PHY Device Family Support
This section describes Deterministic Latency PHY IP core device support.
IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions:
- Final support—Verified with final timing models for this device.
- Preliminary support—Verified with preliminary timing models for this device.
|Arria V devices||Final|
|Arria V GZ devices||Final|
|Cyclone V devices||Final|
|Stratix V devices||Final|
|Other device families||No support|
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