V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

21. Migrating from Stratix IV to Stratix V Devices Overview

Previously, Altera provided the ALTGX megafunction as a general purpose transceiver PHY solution. The current release of the Intel® Quartus® Prime software includes protocol-specific PHY IP cores that simplify the parameterization process.

The design of these protocol-specific transceiver PHYs is modular and uses standard interfaces. An Avalon-MM interface provides access to control and status registers that record the status of the PCS and PMA modules. Consequently, you no longer must include signals in the top level of your transceiver PHY to determine the status of the serial RX and TX interfaces. Using standard interfaces to access this device-dependent information should ease future migrations to other device families and reduce the overall design complexity. However, to facilitate debugging, you may still choose to include some device-dependent signals in the top level of your design during the initial simulations or even permanently. All protocol-specific PHY IP in Stratix V devices also include embedded controls for post-reset initialization which are available through the Avalon-MM interface.

For Stratix IV devices, the location of the transceiver dynamic reconfiguration logic is design dependent. In general, reconfiguration logic is integrated with the transceiver channels for simple configurations and is separately instantiated for more complex designs that use a large number of channels or instantiate more than one protocol in a single transceiver quad. For Stratix V devices, transceiver dynamic reconfiguration is always performed using the separately instantiated Transceiver Reconfiguration Controller.

Control of loopback modes is also different in Stratix IV and Stratix V devices. For Stratix IV devices, you must select loopback options in the using the MegaWizard Plug-In Manager. For Stratix V devices, you control loopback modes through Avalon-MM registers.

Table 354.  Controlling Loopback Modes in Stratix IV and Stratix V Devices
Loopback Mode Stratix IV Stratix V
Serial loopback On the Loopback tab of the ALTGX MegaWizard Plug-In Manager, Instantiate the rx_seriallpbken signal by selecting the Serial loopback option. Drive this signal to 1 to put the transceiver in serial loopback mode. Use the Avalon-MM PHY management interface to set the appropriate bit in the phy_serial_loopback register (0x061).
Reverse serial loopback (pre- and post-CDR) On the Loopback tab of the ALTGX MegaWizard Plug-In Manager, select either pre-CDR or post-CDR loopback and regenerate the ALTGX IP core. Update the appropriate bits of the Transceiver Reconfiguration Controller tx_rx_word_offset register to enable the pre- or post-CDR reverse serial loopback mode. Refer to PMA Analog Registers for more information.

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