V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

10.3.6. PLL Reconfiguration Parameters

Table 131.  PLL Reconfigurations
Name Value Description
Allow PLL Reconfiguration On/Off You must enable this option if you plan to reconfigure the PLLs in your design. This option is also required to simulate PLL reconfiguration.
Number of TX PLLs 1-4

Specifies the number of TX PLLs that can be used to dynamically reconfigure channels to run at multiple data rates. If your design does not require transceiver TX PLL dynamic reconfiguration, set this value to 1. The number of actual physical PLLs that are implemented depends on the selected clock network. Each channel can dynamically select between n PLLs, where n is the number of PLLs specified for this parameter.

You must disable the embedded reset controller and design your own controlled reset controller or the use the highly configurable reset core described in "Transceiver Reconfiguration Controller IP Core" if you intend to use more than 1 TX PLL for a Custom PHY IP instance.

Note: For more details, refer to the Transceiver Clocking chapter in the device handbook for the device family you are using.
Number of reference clocks 1-5 Specifies the number of input reference clocks. More than one reference clock may be required if your design reconfigures channels to run at multiple frequencies.
Main TX PLL logical index 0-3 Specifies the index for the TX PLL that should be instantiated at startup. Logical index 0 corresponds to TX PLL0, and so on.
CDR PLL input clock source 0-3 Specifies the index for the CDR PLL input clock that should be instantiated at startup. Logical index 0 corresponds to input clock 0 and so on.
TX PLL (0-3)
PLL Type

CMU

ATX

Specifies the PLL type.
PLL base data rate

1 × Lane rate

2 × Lane rate

4 × Lane rate

Specifies Base data rate.
Reference clock frequency Variable Specifies the frequency of the PLL input reference clock. The PLL must generate an output frequency that equals the Base data rate/2. You can use any Input clock frequency that allows the PLLs to generate this output frequency.
Selected reference clock source 0-4 Specifies the index of the input clock for this TX PLL. Logical index 0 corresponds to input clock 0 and so on.
Channel Interface
Enable channel interface On/Off Turn this option on to enable PLL and datapath dynamic reconfiguration. When you select this option, the width of tx_parallel_data and rx_parallel_data buses increases in the following way.
  • n The tx_parallel_data bus is 44 bits per lane; however, only the low‑order number of bits specified by the FPGA fabric transceiver interface width contain valid data for each lane.
  • n The rx_parallel_data bus is 64 bits per lane; however, only the low‑order number of bits specified by the FPGA fabric transceiver interface width contain valid data.

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