8.4. Interlaken PHY Optional Port Parameters
|Enable RX status signals, (word lock, sync lock, crc32 error) as part of rx_parallel_data||On/Off||When you turn this option on, rx_parallel_data[71:69] are included in the top-level module. These optional signals report the status of word and synchronization locks and CRC32 errors. Refer to Avalon-ST RX Signals for more information.|
|Create tx_coreclkin port||On/Off||
The tx_coreclkin drives the write side of TX FIFO. This clock is required for multi-lane synchronization but is optional for single lane Interlaken links.
If tx_coreclkin is deselected for single lane Interlaken links, tx_user_clkout drives the TX side of the write FIFO. You must use the tx_user_clkout output port to drive transmit data in the Interlaken MAC.
|Create rx_coreclkin port||On/Off||When selected rx_coreclkin is available as input port which drives the read side of RX FIFO, When deselected rx_user_clkout, rx_clkout for all bonded receiver lanes, is routed internally to drive the RX read side of FIFO. rx_user_clkout is also available as an output port for the Interlaken MAC.|