V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

10.4.5. Register Interface and Register Descriptions

The Avalon-MM PHY management interface provides access to the Custom PHY PCS and PMA registers, resets, error handling, and serial loopback controls. You can use an embedded controller acting as an Avalon-MM master to send read and write commands to this Avalon-MM slave interface.
Figure 55. Custom PHY IP Core

Table 141.   Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk Input Avalon-MM clock input. There is no frequency restriction for the phy_mgmt_clk; however, if you plan to use the same clock for the PHY management interface and transceiver reconfiguration, you must restrict the frequency range of phy_mgmt_clk to 100-150 MHz to meet the specification for the transceiver reconfiguration clock.
phy_mgmt_clk_reset Input Global reset signal. This signal is active high and level sensitive.
phy_mgmt_address[8:0] Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0] Input Input data.
phy_mgmt_readdata[31:0] Output Output data.
phy_mgmt_write Input Write signal.
phy_mgmt_read Input Read signal.
phy_mgmt_waitrequest Output When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.

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