V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

13.5. Interfaces for Stratix V Native PHY

This section describes the common, Standard and 10G PCS interfaces for the Stratix V Native PHY.

The Native PHY includes several interfaces that are common to all parameterizations. It also has separate interfaces for the Standard and 10G PCS datapaths. If you use dynamic reconfiguration to change between the Standard and 10G PCS datapaths, your top-level HDL file includes the port for both the Standard and 10G PCS datapaths. In addition, the Native PHY allows you to enable ports, even for disabled blocks to facilitate dynamic reconfiguration.

The Native PHY uses the following prefixes for port names:

  • Standard PCS ports—tx_std_, rx_std_
  • 10G PCS ports—tx_10g_, rx_10g_
  • PMA ports—tx_pma_, rx_pma_

The port descriptions use the following variables to represent parameters:

  • <n>—The number of lanes
  • <p>—The number of PLLs
  • <r>—the number of CDR references clocks selected

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