V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

6.3.1. Register Map

You can access the 16-bit/32-bit configuration registers via the Avalon® memory-mapped interface.

Table 73.  Register Map
Address Range Usage Bit Configuration
0x00 : 0x1F 1000BASE-X/SGMII 16 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE-T)
0x400 : 0x41F USXGMII 32 10M/100M/1G/2.5G/5G/10G (USXGMII)
0x461 Serial Loopback 32 10M/100M/1G/2.5G/5G/10G (USXGMII)