14.9. Dynamic Reconfiguration
As silicon progresses towards smaller process nodes, circuit performance is affected more by variations due to process, voltage, and temperature (PVT). These process variations result in analog voltages that can be offset from required ranges. The calibration performed by the dynamic reconfiguration interface compensates for variations due to PVT.
For nonbonded clocks, each channel and each TX PLL has a separate dynamic reconfiguration interfaces. The MegaWizard Plug-In Manager provides informational messages on the connectivity of these interfaces. The following example shows the messages for the Arria V Native PHY with four duplex channels, four TX PLLs, in a nonbonded configuration.
For more information about transceiver reconfiguration refer to Transceiver Reconfiguration Controller IP Core.
Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 8 reconfiguration interfaces for connection to the external reconfiguration controller. Reconfiguration interface offsets 0-3 are connected to the transceiver channels. Reconfiguration interface offsets 4–7 are connected to the transmit PLLs.
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