9.11. PHY for PCIe (PIPE) Serial Data Interface
|rx_serial_data[<n>-1:0]||Input||Receiver differential serial input data, <n> is the number of lanes.|
|tx_serial_data[<n>-1:0]||Output||Transmitter differential serial output data <n> is the number of lanes.|
For information about channel placement, refer to “Transceiver Clocking and Channel Placement Guidelines” in the Transceiver Configurations in Arria V GZ Devices or “Transceiver Clocking and Channel Placement Guidelines” in the Transceiver Configurations in Stratix V Devices as appropriate.
For information about channel placement of the Hard IP PCI Express IP Core, refer to the Channel Placement Gen1 and Gen2 and Channel Placement Gen3 sections in the Stratix V Hard IP for PCI Express User Guide.
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