V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

21.7. Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices

This section lists the differences between the top-level signals in Stratix IV GX and Stratix V GX/GS devices.
Table 360.  Custom PHY Correspondences between Stratix IV GX Device and Stratix V Device Signals
ALTGX24 Custom PHY Width
Avalon-MM Management Interface
Not available phy_mgmt_clk_reset 1
phy_mgmt_clk 1
phy_mgmt_address 8
phy_mgmt_read 1
phy_mgmt_readdata 32
phy_mgmt_write 1
phy_mgmt_writedata 32
Clocks
cal_blk_clk These signals are included in the reconfig_to_xcvr bus
reconfig_clk
pll_inclk pll_ref_clk [<p>-1:0]
rx_coreclk rx_coreclkin
tx_coreclk tx_coreclkin
Avalon-ST TX Interface
tx_datain tx_parallel_data [<d><n>-1:0]
tx_ctrlenable tx_datak [<d><n>-1:0]
rx_ctrldetect rx_datak [<d><n>-1:0]
Avalon-ST RX Interface
rx_dataout rx_parallel_data [<d><n>-1:0]
rx_runningdisp rx_runningdisp [<d/8><n>-1:0]
rx_enabyteord rx_enabyteord [<n>-1:0]
High Speed Serial I/O
rx_datain rx_serial_data [<n>-1:0]
tx_dataout tx_serial_data [<n>-1:0]
rx_freqlocked rx_is_lockedtodata [<n>-1:0]
Transceiver Control and Status Signals
gxb_powerdown phy_mgmt_clk_reset
rx_dataoutfull
tx_dataoutfull
rx_pll_locked There are both pll_locked and rx_pll_clocked in Stratix IV. Stratix V only has pll_locked.
rx_clkout These signals are now available as control and status registers. Refer to Register Descriptions.
rx_phase_comp_fifo_error
rx_seriallpbken
tx_phase_comp_fifo_error
tx_invpolarity
Transceiver Reconfiguration
reconfig_togxb[3:0] reconfig_to_xcvr Variable
reconfig_fromgxb[16:0] reconfig_from_xcvr Variable
24 <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.

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