8. Interlaken PHY IP Core
Interlaken is a high speed serial communication protocol for chip-to-chip packet transfers. It supports multiple instances, each with 1 to 24 lanes running at 10.3125 Gbps or greater in Arria V GZ and Stratix V devices. The key advantages of Interlaken are scalability and its low I/O count compared to earlier protocols such as SPI 4.2. Other key features include flow control, low overhead framing, and extensive integrity checking. The Interlaken physical coding sublayer (PCS) transmits and receives Avalon-ST data on its FPGA fabric interface. It transmits and receives high speed differential serial data using the PCML I/O standard.
For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon Interface Specifications.
Interlaken operates on 64-bit data words and 3 control bits, which are striped round robin across the lanes to reduce latency. Striping renders the interface independent of exact lane count. The protocol accepts packets on 256 logical channels and is expandable to accommodate up to 65,536 logical channels. Packets are split into small bursts which can optionally be interleaved. The burst semantics include integrity checking and per channel flow control.
The Interlaken PCS supports the following framing functions on a per lane basis:
- Block synchronization
- Metaframe generation and synchronizatio
- 64b/67b encoding and decoding
- Scrambling and descrambling
- Lane-based CRC32
- Disparity DC balancing
For more detailed information about the Interlaken transceiver channel datapath, clocking, and channel placement in Stratix V devices, refer to the “Interlaken” section in the Transceiver Configurations in Stratix V Devices chapter of the Stratix V Device Handbook.
For more detailed information about the Interlaken transceiver channel datapath, clocking, and channel placement in Arria V GZ devices, refer to the “Interlaken” section in the Transceiver Configurations in Arria V Devices chapter of the Arria V Device Handbook.
Refer to PHY IP Design Flow with Interlaken for Stratix V Devices for a reference design that implements the Interlaken protocol in a Stratix V device.
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