3.15. 10GBASE-R PHY Clocks for Stratix IV Devices
The phy_mgmt_clk_reset signal is the global reset that resets the entire PHY. A positive edge on this signal triggers a reset.
Refer to the Reset Control and Power Down chapter in volume 2 of the Stratix IV Device Handbook for additional information about reset sequences in Stratix IV devices.
The PCS runs at 257.8125 MHz using the pma_rx_clock provided by the PMA. You must provide the PMA an input reference clock running at 644.53725 MHz to generate the 257.8125 MHz clock.
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