V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Document Table of Contents

3.15. 10GBASE-R PHY Clocks for Stratix IV Devices

The phy_mgmt_clk_reset signal is the global reset that resets the entire PHY. A positive edge on this signal triggers a reset.

Refer to the Reset Control and Power Down chapter in volume 2 of the Stratix IV Device Handbook for additional information about reset sequences in Stratix IV devices.

The PCS runs at 257.8125 MHz using the pma_rx_clock provided by the PMA. You must provide the PMA an input reference clock running at 644.53725 MHz to generate the 257.8125 MHz clock.

Figure 14. Stratix IV Clock Generation and Distribution